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document no. 70-0235-07 www.psemi.com page 1 of 14 ?2010-2013 peregrine semiconductor corp. all rights reserved. peregrine?s PE97022 is a high-performance integer-n pll capable of frequency synthesis up to 3.5 ghz. the device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space plls. the PE97022 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in figure 1 . counter values are programmable through either a serial or parallel interface and can also be directly hardwired. the PE97022 is optimized for commercial space applications. single event latch-up (sel) is physically impossible and single event upset (seu) is better than 10 -9 errors per bit / day. it is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate, offering excellent rf performance and intrinsic radiation tolerance. product specification 3.5 ghz ultracmos ? integer-n pll rad hard for space applications product description PE97022 features ?? low power - 45 ma at 3.3 v ?? 3.5 ghz operation ?? 10/11 dual modulus prescaler ?? internal phase detector ?? serial, parallel, or direct hardwired mode ?? ultra-low phase noise: -216 dbc/hz ?? seu < 10 -9 errors / bit-day ?? 100 krad (si) total dose ?? pin compatible with the pe9702, packaged in a 44-lead cqfj (reference application note an22 at www.psemi.com) figure 1. block diagram
product specification PE97022 page 2 of 14 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0235-07 ultracmos ? rfic solutions table 1. pin descriptions figure 2. pin configurations (top view) 44-lead cqfj figure 3. package type f in f in hop_wr a_wr m1_wr v dd bmode smode, a 3 m2_wr, a 2 e_wr, a 1 fselp, a 0 gnd r 3 r 2 r 1 r 0 v dd enh ld fr gnd gnd pin no. pin name interface mode type description 1 v dd all (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 2 r 0 direct input r counter bit0 (lsb). 3 r 1 direct input r counter bit1. 4 r 2 direct input r counter bit2. 5 r 3 direct input r counter bit3. 6 gnd all ground. 7 d 0 parallel input parallel data bus bit0 (lsb). m 0 direct input m counter bit0 (lsb). 8 d 1 parallel input parallel data bus bit1. m 1 direct input m counter bit1. 9 d 2 parallel input parallel data bus bit2. m 2 direct input m counter bit2. 10 d 3 parallel input parallel data bus bit3. m 3 direct input m counter bit3. 11 v dd all (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 12 v dd all (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 13 s_wr serial input serial load enable input. while s_wr is ?low?, sdata can be serially clocked. primary register data is transferred to the sec ondary register on s_wr or hop_wr rising edge. d 4 parallel input parallel data bus bit4 m 4 direct input m counter bit4
product specification PE97022 page 3 of 14 document no. 70-0235-07 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. 14 sdata serial input binary serial data input. input data entered msb first. d 5 parallel input parallel data bus bit5. m 5 direct input m counter bit5. 15 sclk serial input serial clock input. sdata is clocked seria lly into the 20-bit primary register (e_wr ?low?) or the 8-bit enhancement register (e _wr ?high?) on the rising edge of sclk. d 6 parallel input parallel data bus bit6. m 6 direct input m counter bit6. 16 fsels serial input selects contents of primary register (fsels = 1) or se condary register (fsels = 0) for programming of internal counters while in serial interface mode. d 7 parallel input parallel data bus bit7 (msb). pre_en direct input prescaler enable, active ?low?. when ?high?, f in bypasses the prescaler. 17 gnd all ground. 18 fselp parallel input selects contents of primary register (fselp=1) or sec ondary register (fselp = 0) for programming of internal counters while in parallel interface mode. a 0 direct input a counter bit0 (lsb). 19 e_wr serial input enhancement register write enable. while e_ wr is ?high?, sdata can be serially clocked into the enhancement regi ster on the rising edge of sclk. parallel input enhancement register write. d[7:0] are latched into the enhancement register on the rising edge of e_wr. a 1 direct input a counter bit1. 20 m2_wr parallel input m2 write. d[3:0] are latched into the primary register (r[5:4], m[8:7]) on the rising edge of m2_wr. a 2 direct input a counter bit2. 21 smode serial, parallel input selects serial bus interface mode ( bmode = 0, smode = 1) or parallel interface mode ( bmode = 0, smode = 0). a 3 direct input a counter bit3 (msb). 22 bmode all input selects direct interface mode ( bmode = 1). 23 v dd all (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 24 m1_wr parallel input m1 write. d[7:0] are latched into the primary register ( pre_en , m[6:0]) on the rising edge of m1_wr. 25 a_wr parallel input a write. d[7:0] are latched into the primary register (r[3:0], a[3:0]) on the rising edge of a_wr. 26 hop_wr serial, parallel input hop write. the contents of the primary register are latched into the secondary register on the rising edge of hop_wr. 27 f in all input prescaler input from the vco, 3.5 ghz max frequency. a 22 pf coupling capacitor should be placed as close as possible to this pi n and terminated with a 50 ? resistor to ground. 28 f ? in all input prescaler complementary input. a 22 pf by pass capacitor should be placed as close as possible to this pin and be connected in series with a 50 resistor to ground. 29 gnd all ground. 30 f p all output monitor pin for main divider output. sw itching activity can be disabled through enhancement register programming or by floating or grounding v dd pin 31. table 1. pin descriptions (continued) pin no. pin name interface mode type description
product specification PE97022 page 4 of 14 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0235-07 ultracmos ? rfic solutions table 1. pin descriptions (continued) notes: 1. v dd pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by di odes and must be supplied with the same positive voltage level. v dd pins 31 and 38 are used to enable te st modes and should be left floating. 2. all digital input pins have 70 k ? pull-down resistors to ground. pin no. pin name interface mode type description 31 v dd -f p all (note 1) v dd for f p . can be left floating or connec ted to gnd to disable the f p output. 32 dout serial, parallel output data out. the msel signal and the raw prescaler output are available on dout through enhancement register programming. 33 v dd all (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 34 c ext all output logical ?nand? of pd_ u and pd_ d terminated through an on chip, 2 k ? series resistor. connecting c ext to an external capacitor will low pass filter the input to the inverting amplifier used for driving ld. 35 v dd all (note 1) power supply input. input may range from 2.85 v to 3.45 v. bypassing recommended. 36 pd_ u all output pd_ d is pulse down when f p leads f c . 37 pd_ u all pd_ u is pulse down when f c leads f p . 38 v dd -f c all (note 1) v dd for f c . can be left floating or connect ed to gnd to disable the f c output. 39 f c all output monitor pin for reference divider output. switching activity can be disabled through enhancement register programming or by floating or grounding v dd pin 38. 40 gnd all ground. 41 gnd all ground. 42 f r all input reference frequency input. 43 ld all output lock detect and open drain logical inversion of c ext . when the loop is in lock, ld is high impedance, otherwise ld is a logic low (?0?). 44 enh serial, parallel input enhancement mode. when asserted low (?0?), enhancement register bits are functional.
product specification PE97022 page 5 of 14 document no. 70-0235-07 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. table 2. absolute maximum ratings note: 1. periodically sampled, not 100% tested. tested per mil-std- 883, m3015 c2 table 4. esd ratings electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating in table 4 . latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. table 3. operating ratings table 5. dc characteristics: v dd = 3.3 v, -40 c < t a < 85 c, unless otherwise specified symbol parameter/conditions min max units v dd supply voltage -0.3 4.0 v v i voltage on any input -0.3 v dd + 0.3 v i i dc into any input -10 +10 ma i o dc into any output -10 +10 ma t stg storage temperature range -65 150 c symbol parameter/conditions level units v esd esd voltage (human body model) 1 1000 v symbol parameter/conditions min max units v dd supply voltage 2.85 3.45 v t a operating ambient temperature range -40 85 c symbol parameter conditions min typ max units i dd operational supply current; v dd = 2.85 to 3.45 v prescaler disabled 15 ma prescaler enabled 45 50 ma digital inputs: all except f r , f in , f in v ih high level input voltage v dd = 2.85 to 3.45 v 0.7 x v dd v v il low level input voltage v dd = 2.85 to 3.45 v 0.3 x v dd v i ih high level input current v ih = v dd = 3.45 v 70 a i il low level input current v il = 0, v dd = 3.45 v -1 a reference divider input: f r i ihr high level input current v ih = v dd = 3.45 v 100 a i ilr low level input current v il = 0, v dd = 3.45 v -100 a counter and phase detector outputs: f c , f p . v old output voltage low i out = 6 ma 0.4 v v ohd output voltage high i out = -3 ma v dd - 0.4 v lock detect outputs: c ext , ld v olc output voltage low, c ext i out = 100 a 0.4 v v ohc output voltage high, c ext i out = -100 a v dd - 0.4 v v olld output voltage low, ld i out = 1 ma 0.4 v
product specification PE97022 page 6 of 14 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0235-07 ultracmos ? rfic solutions table 6. ac characteristics: v dd = 3.3 v, -40 c < t a < 85 c, unless otherwise specified notes: 1. fclk is verified during the func tional pattern test. serial programming sections of the functional pattern are clocke d at 10 mhz to verify fclk specification. 2. cmos logic levels can be used to drive the reference input. if the v dd of the cmos driver matches the v dd of pll ic, then the reference input can be dc coupled. otherwise, the reference i nput should be ac coupled. 3. parameter is guaranteed through characterization only and is not tested. 4. parameters below are not tested for die sales. thes e parameters are verified during the element evaluation. symbol parameter conditions min typical max units control interface and latches (see figures 4, 5, 6 ) f clk serial data clock frequency (note 1) 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t dsu sdata set-up time after sclk rising edge, d[7:0] set-up time to m1_wr, m2_wr, a_wr, e_wr rising edge 10 ns t dhld sdata hold time after sclk rising edge, d[7:0] hold time to m1_wr, m2_wr, a_wr, e_wr rising edge 10 ns t pw s_wr, m1_wr, m2_wr, a_wr, e_wr pulse width 30 ns t cwr sclk rising edge to s_wr rising edge. s_wr, m1_wr, m2_wr, a_wr falling edge to hop_wr rising edge 30 ns t ce sclk falling edge to e_wr transition 30 ns t wrc s_wr falling edge to sclk rising edge. hop_wr fall- ing edge to s_wr, m1_wr, m2_wr, a_wr rising edge 30 ns t ec e_wr transition to sclk rising edge 30 ns t mdo msel data out delay after fin rising edge c l = 12 pf 8 ns main divider (including prescaler) 4 p fin input level range external ac coupling 275 mhz freq 3200mhz -5 5 dbm external ac coupling 3.2 ghz < freq 3.5 ghz 3.15 v v dd 3.45 v 0 5 dbm main divider (prescaler bypassed) 4 f in operating frequency 50 300 mhz p fin input level range external ac coupling -5 5 dbm reference divider f r operating frequency (note 3) 100 mhz p fr reference input power 2 single-ended input -2 10 dbm phase detector f c comparison frequency (note 3) 50 mhz ssb phase noise (f in = 1.9 ghz, f r = 20 mhz, f c = 20 mhz, lbw = 50 khz, v dd = 3.3 v, temp = 25 ? c) 4 ? n phase noise 100 hz offset -89 dbc/hz ? n phase noise 1 khz offset -95 dbc/hz ? n phase noise 10 khz offset -102 dbc/hz ssb phase noise (f in = 1.9 ghz, f r = 20 mhz, f c = 20 mhz, lbw = 50 khz, v dd = 3.0 v, temp = 25 ? c) 4 ? n phase noise 100 hz offset -87 dbc/hz ? n phase noise 1 khz offset -94 dbc/hz ? n phase noise 10 khz offset -101 dbc/hz
product specification PE97022 page 7 of 14 document no. 70-0235-07 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. figure 4. rf sensitivity versus frequency (typical device at temperature = 25 c) -30 -25 -20 -15 -10 -5 0 5 0 500 1000 1500 2000 2500 3000 3500 4000 frequency (mhz) rf sensitivity (dbm) 2.85v 3.15v 3.30v figure 5. typical phase noise for PE97022, v dd = 3.3 v, temp = 25 c, fvco = 1.92 ghz, fcomp = 20 mhz, loop bandwidth = 50 khz
product specification PE97022 page 8 of 14 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0235-07 ultracmos ? rfic solutions functional description the PE97022 consists of a prescaler, counters, a phase detector, and control logic. the dual modulus prescaler divides the vco frequency by either 10 or 11, depending on the value of the modulus select. counters ?r? and ?m? divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. an additional counter (?a?) is used in the modulus select logic. the phase-frequency detector generates up and down frequency control signals. the control logic includes a selectable chip interface. data can be written via serial bus, parallel bus, or hardwired directly to the pins. there are also various operational and test modes and a lock detect output. figure 6. functional block diagram control logic r counter (6-bit) phase detector f c pd_u pd_d ld r(5:0) m(8:0) a (3:0) d(7:0) sdata control pins f r modulus select 10/11 prescaler m counter (9-bit) cext f p f in f in
product specification PE97022 page 9 of 14 document no. 70-0235-07 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. figure 7. equivalent input diagram: reference input figure 9. equivalent input diagram: pd _ d & pd _ u outputs pin 42 peregrine specification 71/0032 peregrine specification 71/0033 pin 27 pin 28 pin 36 pin 37 figure 8. equivalent input diagram: main input peregrine specification 71/0034
product specification PE97022 page 10 of 14 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0235-07 ultracmos ? rfic solutions main counter chain normal operating mode the main counter chain divides the rf input frequency, f in , by an integer derived from the user -defined values in the ?m? and ?a? counters. it is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9-bit m counter. setting pre_en ?low? enables the 10/11 prescaler. setting pre_en ?high? allows f in to bypass the prescaler and powers down the prescaler. the output from the main counter chain, f p , is related to the vco frequency, f in , by the following equation: f p = f in / [10 x (m + 1) + a] (1) where a ? m + 1, 1 m 511 when the loop is locked, f in is related to the reference frequency, f r , by the following equation: f in = [10 x (m + 1) + a] x (f r / (r+1)) (2) where a ? m + 1, 1 m 511 a consequence of the upper limit on a is that f in must be greater than or equal to 90 x (f r / (r+1)) to obtain contiguous channels. programming the m counter with the minimum value of ?1? will result in a minimum m counter divide ratio of ?2?. in direct interface mode, main counter inputs m 7 and m 8 are internally forced low. in this mode, the m value is limited to 1 m 127. prescaler bypass mode setting pre_en ?high? allows f in to bypass and power down the prescaler. in this mode, the 10/11 prescaler and a register are not active, and the input vco frequency is divided by the m counter directly. the following equation relates f in to the reference frequency, f r : f in = (m + 1) x (f r / (r+1)) ) (3) where 1 m 511 in direct interface mode, main counter inputs m 7 and m 8 are internally forced low. in this mode, the m value is limited to 1 m 127. reference counter the reference counter chain divides the reference frequency, f r , down to the phase detector comparison frequency, f c . the output frequency of the 6-bit r counter is related to the reference frequency by the following equation: f c = f r / (r + 1) (4) where 0 r 63 note that programming r with ?0? will pass the reference frequency, f r , directly to the phase detector. in direct interface mode, r counter inputs r 4 and r 5 are internally forced low (?0?). in this mode, the r value is limited to 0 r 15. register programming parallel interface mode parallel interface mode is selected by setting the bmode input ?low? and the smode input ?low?. parallel input data, d[7:0], are latched in a parallel fashion into one of three 8-bit primary register sections on the rising edge of m1_wr, m2_wr, or a_wr per the mapping shown in table 7 on page 11. the contents of the primary register are transferred into a secondary register on the rising edge of hop_wr according to the timing diagram shown in figure 10 . data is transferred to the counters as shown in table 7 on page 11. the secondary register acts as a buffer to allow rapid changes to the vco frequency. this double buffering for ?ping-pong? counter control is programmed via the fselp input. when fselp is ?high?, the primary register contents set the counter inputs. when fselp is ?low?, the secondary register contents are utilized. parallel input data, d[7:0], are latched into the enhancement register on the rising edge of e_wr according to the timing diagram shown in figure 10. this data provides control bits as shown in table 8 on page 11 with bit functionality enabled by asserting the enh input ?low?.
product specification PE97022 page 11 of 14 document no. 70-0235-07 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. serial interface mode serial interface mode is selected by setting the bmode input ?low? and the smode input ?high?. while the e_wr input is ?low? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 19 , is clocked serially into the primary register on the rising edge of sclk, msb (b 0 ) first. the contents from the primary register are transferred into the secondary register on the rising edge of either s_wr or hop_wr according to the timing diagram shown in figure 11. data is transferred to the counters as shown in table 7 . the double buffering provided by the primary and secondary registers allows for ?ping-pong? counter control using the fsels input. when fsels is ?high?, the primary register contents set the counter inputs. when fsels is ?low?, the secondary register contents are utilized. while the e_wr input is ?high? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 7 , is clocked serially into the enhancement register on the rising edge of sclk, msb (b 0 ) first. the enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially-entered data performed on the falling edge of e_wr according to the timing diagram shown in figure 11 . after the falling edge of e_wr, the data provides control bits as shown in table 8 with bit functionality enabled by asserting the enh input ?low?. direct interface mode direct interface mode is selected by setting the bmode input ?high?. counter control bits are set directly at the pins as shown in table 7 . in direct interface mode, main counter inputs m 7 and m 8 , and r counter inputs r 4 and r 5 are internally forced low (?0?). msb (first in) (last in) lsb table 7. primary register programming table 8. enhancement register programming *serial data clocked serially on sclk rising edge while e_wr ?low? and captured in secondary register on s_wr rising edge. *serial data clocked serially on sclk rising edge while e_wr ?high? and captured in the double buffer on e_wr falling edge. msb (first in) (last in) lsb interface mode enh bmode smode r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 parallel 1 0 0 m2_wr rising edge load m1_wr rising edge load a_wr rising edge load d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 serial* 1 0 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 direct 1 1 x 0 0 0 0 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 interface mode enh bmode smode reserved reserved reserved power down counter load msel output prescaler output f c , f p oe parallel 0 0 0 e_wr rising edge load d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 serial* 0 0 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7
product specification PE97022 page 12 of 14 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0235-07 ultracmos ? rfic solutions figure 11. serial interface mode timing diagram figure 10. parallel interface mode timing diagram ?? 0 : 7
product specification PE97022 page 13 of 14 document no. 70-0235-07 www.psemi.com ?2010-2013 peregrine semiconductor corp. all rights reserved. a lock detect output, ld is also provided, via the pin c ext . c ext is the logical ?nand? of pd_ u and pd_ d waveforms, which is driven through a series 2k ? resistor. connecting c ext to an external shunt capacitor provides integration. c ext also drives the input of an internal inverting comparator with an open drain output. thus ld is an ?and? function of pd_ u and pd_ d . see figure 6 for a schematic of this circuit. enhancement register the functions of the enhancement register bits ar e shown below with all bits active ?high?. table 9. enhancement register bit functionality ** program to 0 phase detector the phase detector is triggered by rising edges from the main counter (f p ) and the reference counter (f c ). it has two outputs, namely pd_ u , and pd_ d . if the divided vco leads the divided reference in phase or frequency (f p leads f c ), pd_ d pulses ?low?. if the divided reference leads the divided vco in phase or frequency (f r leads f p ), pd_ u pulses ?low?. the width of either pulse is directly proportional to phase offset between the two input signals, f p and f c . the phase detector gain is 430 mv / radian. pd_ u and pd_ d are designed to drive an active loop filter which controls the vco tune voltage. pd_ u pulses result in an increase in vco frequency and pd_ d results in a decrease in vco frequency. bit function description bit 0 reserved** bit 1 reserved** bit 2 reserved** bit 3 power down power down of all functions except programming interface. bit 4 counter load immediate and continuous load of counter programming as directed by the bmode and smode inputs. bit 5 msel output drives the intern al dual modulus prescaler modulus select (msel) onto the dout output. bit 6 prescaler output drives the raw internal prescaler output (fmain) onto the dout output. bit 7 f p , f c oe f p , f c outputs disabled.
product specification PE97022 page 14 of 14 ?2010-2013 peregrine semiconductor corp. all rights reserved. document no. 70-0235-07 ultracmos ? rfic solutions figure 12. package drawing 44-lead cqfj table 10. ordering information all dimensions are in inches order code part marking description package shipping method 97022-01 PE97022 es engineering samples 44-pin cqfj 40 units / tray 97022-11 PE97022 flight units 44-pin cqfj 40 units / tray 97022-00 PE97022 ek evaluation kit 1 / box 97022-99 fa97022 die production units die 100 units / waffle pack advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in dev ices or systems int ended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for dam ages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. sales contact and information for sales and contact information please visit www.psemi.com.

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